The present invention relates to the fabrication of semiconductor devices. More specifically, the present invention relates to a method of fabricating a semiconductor device that includes both self aligned silicide active regions and non-self aligned silicide active regions.
In many semiconductor applications, different types of transistors are fabricated on a single semiconductor wafer. For example, in memory applications, memory transistors and logic transistors are fabricated on a single semiconductor wafer. Typically, different types of transistors are fabricated in different regions of the wafer. For example, in a memory chip, logic transistors are fabricated in a first region, while the memory transistors are fabricated in a second region of the wafer. However, in many applications different types of transistors are interspersed among each other on the wafer. For example, on some wafers, the memory transistors are fabricated as part of a fieldless array. A fieldless array is defined as an array that does not use field oxide to isolate the various elements of the array. Because field oxide is not required to isolate the memory transistors in a fieldless array, the memory transistors can be laid out with a relatively high density. However, conventional CMOS devices (e.g., transistors) are fabricated among the memory transistors, but do not form part of the fieldless array.
It may be difficult to achieve an acceptable yield when fabricating different types of transistors on the same wafer. For example, conventional salicide (self-aligned silicide) techniques for gate electrodes and actives regions in one type of transistor may cause shorts in a second type of transistor. Specifically, conventional salicide techniques may result in electrical short circuits between the source and drain regions of fieldless array transistors. These short circuits may exist for the following reason. During the formation of logic transistors, an etch is performed to create the sidewall spacers of the logic transistors. This etch can expose the silicon between the source and drain regions of the fieldless array transistors. To reduce the resistance of the gate structures of the transistors, a refractory metal is subsequently deposited over the upper surface of the wafer to form self-aligned silicide or xe2x80x9csalicidexe2x80x9d gate electrodes. A silicide layer is formed by reacting this refractory metal with exposed silicon. Thus, a silicide layer forms between the source and drain regions of the fieldless array transistors, thereby causing a short circuit. It would therefore be desirable to have a method for fabricating transistors having salicide gate and active regions as well as transistors with salicide gate but without salicide active regions on the same wafer. For clarity, the term xe2x80x9cfully-salicided transistorxe2x80x9d refers to a transistor having low resistance salicide on the gate and active regions of the transistor. Conversely, the term xe2x80x9cpartially-salicided transistorxe2x80x9d refers to a transistor having low resistance salicide only on the gate of the transistor.
Accordingly, the present invention provides efficient processes for fabricating fully-salicided transistors and partially salicided transistors on the same wafer. A fully-salicided transistor includes silicide on the gate and active regions of the transistor. A partially-salicided transistor has silicide on the gate of the transistor but not on the active regions.
Specifically, in accordance with one embodiment of, the present invention, fully-salicided transistors are formed in a first region of the semiconductor device, while partially-salicided transistors are formed in a second region of the semiconductor device. Conductive gates are formed in both the first region and the second region of the semiconductor device. Then, active regions for the transistors are formed in the first region and second region of the semiconductor device. Different techniques and processing steps may be used to form the active regions in the first region of the semiconductor device and the active regions in the second region of the semiconductor device.
A first thin dielectric layer is deposited over the surface of the semiconductor device. Then, a second thin dielectric layer is deposited over the semiconductor device. The second dielectric layer is an etch stop layer, such as a nitride layer. A thick silicide blocking layer is deposited over the second thin dielectric layer. A portion of the thick silicide blocking layer in the first region of the semiconductor device is etched to expose the second thin dielectric layer in the first region of the semiconductor device. An oxide spacer layer is deposited over the semiconductor device and etched back to form oxide spacers and remove the thin dielectric layers in the first region of the semiconductor device. Then, salicide layers are formed over the active regions in the first region of the semiconductor device and the conductive gates.
The above-described process steps advantageously enable fully-salicided transistors and partially-salicided transistors on the same semiconductor device. The present invention will be more fully understood in view of the following description and drawings.